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as1106, as1107 8-digit led display drivers www.austriamicrosystems.com revision 2.2 1 - 20 austria micro systems data sheet 1 general description the as1106 and the as1107 are compact display driv- ers for 7-segment numeric displays of up to 8 digits. the devices can be programmed via spi, qspi, and microw- ire as well as a conventional 4-wire serial interface. the devices include an in tegrated bcd code-b/hex decoder, multiplex scan circuitry, segment and display drivers, and a 64-bit memory. internal memory stores the led settings, eliminating the need for continuous device reprogramming. every segment can be individually addressed and updated separately. only one external resistor (r set ) is required to set the current through the led display. led brightness can be controlled by analog or digital means. the devices can be programmed to use the internal code-b/hex decoder to display numeric digits or to directly address each segment. the as1106 and the as1107 feature an extremely low shutdown current of typically 3a, and an operational current of less than 500a. the number of digits can be programmed, the devices can be reset by software, and an external clock is also supported. additionally, seg- ment blinking can be synchronized across multiple driv- ers. several test modes are available for easy application debugging. the devices are available in 24-pin dip and 24-pin soic packages. figure 1. typical application diagram 2 key features 10mhz spi-, qspi-, mi crowire-compatible serial i/o individual led segment control segment blinking control (can be synchronized across multiple drivers) hexadecimal- or bcd-code/no-decode digit selection 3a low-power shutdown current (typ; data retained) extremely low operating current 0.5ma in open- loop digital and analog brightness control display blanked on power-up drive common-cathode led displays low-emi low slew-rate limited segment drivers (as1107) supply voltage range: 2.7 to 5.5v software reset optional external clock packages: - 24-pin dip - 24-pin soic 3 applications the as1106 and as1107 are ideal for bar-graph dis- plays, instrument-panel meters, led matrix displays, dot matrix displays, set-top boxe s, white goods, professional audio equipment, medical equipment, industrial control- lers and panel meters. as1106/ as1107 8-digit microprocessor display dig0 to dig7 seg a to g sep dp 8 digits 8 segments i/o i/o sck v dd i set din clk gnd gnd load/csn +5v 9.53k micro- processor
www.austriamicrosystems.com revision 2.2 2 - 20 as1106, as1107 austria micro systems data sheet 4 absolute maximum ratings stresses beyond those listed in table 1 may cause perm anent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond t hose indicated in section 5 electrical characteristics on page 3 is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. table 1. absolute maximum ratings parameter min max units notes voltage (with respect to gnd) v dd -0.3 7 v din, clk, load/csn -0.3 7 v all other pins -0.3 7 or v dd + 0.3 v current dig 0:dig 7 sink current 500 ma seg a:seg g, seg dp 100 ma continuous power dissipation (t amb = +85oc) narrow plastic dip 1066 mw derate 13.3mw/oc above +70oc wide soic 941 mw derate 11.8mw/oc above +70oc operating temperature ranges (t min tot max ) as1106pl, as1106wl 0 +70 oc as1106pe, as1106we -40 +85 oc AS1107PL, as1107wl 0 +70 oc storage temperature range -65 +150 oc package body temperature (wide soic) 1 1. the reflow peak soldering temperature (body temperature) is specified according to ipc/jedec j-std-020c ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices? . +260 oc soldering temperature (narrow dip) 2 2. specified according jesd22-b106 ?resistance to soldering temp erature for through-hole mounted devices? . +260 oc humidity 5 85 % non-condensing electrostatic discharge 3 3. norm: mil 883 e method 3015 . digital outputs 1000 v all other pins 1000 v latch-up immunity 4 4. norm: jedec 17 . 200 ma all pins except as1106 pin 14: 180 ma
www.austriamicrosystems.com revision 2.2 3 - 20 as1106, as1107 austria micro systems data sheet 5 electrical characteristics conditions: v dd = 2.7 to 5.5v, r set = 9.53k 1%, t amb = t min to t max (unless otherwise specified). table 2. electrical characteristics parameter symbol conditions min typ max unit operating supply voltage v dd 2.7 5.0 5.5 v shutdown supply current i ddsd all digital inputs at v dd or gnd, t amb = +25oc 10 a operating supply current i dd r set = open circuit. 1 ma all segments and decimal point on; i seg = -40ma. 330 display scan rate f osc 8 digits scanned 500 800 1300 hz digit drive sink current i digit v out = 0.65v 320 ma segment drive source current i seg v dd = 5.0v, v out = (v dd -1v) -30 -40 -45 ma segment current slew rate (as1107 only) i seg / t t amb = +25oc, v dd = 5.0v, v out = (v dd -1v) 10 20 50 ma/s segment drive current matching i seg 3.0 % digit drive leakage (as1107 only) i digit digit off, v digit = v dd -10 a segment drive leakage (as1107 only) i seg segment off, v seg = 0v 1a digit drive source current (as1106 only) i digit digit off, v digit = (v dd - 0.3v) -2 ma segment drive sink current (as1106 only) i seg segment off, v seg = 0.3v 5ma slow segment blink period (on phase, internal oscillator) t slowblink 0.64 1 1.65 s fast segment blink period (on phase, internal oscillator) t fastblink 0.32 0.5 0.83 s fast or slow segment blink duty cycle (guaranteed by design) 49.9 50 50.1 % table 3. logic inputs/outputs characteristics parameter symbol conditions min typ max unit input current din, clk, load/csn i ih , i il v in = 0v or v dd -1 1 a logic high input voltage v ih 0.7 x v dd v logic low input voltage v il v dd = 5.0v 10% 0.8 v v dd = 3.0v 10% 0.6 output high voltage v oh dout, i source = -1ma, v dd = 5.0v 10% v dd - 1 v dout, i source = -1ma, v dd = 3.0v 10% v dd - 0.5 output low voltage v ol dout, i sink = 1.6ma 0.4 v hysteresis voltage v i din, clk, load/csn 1 v
www.austriamicrosystems.com revision 2.2 4 - 20 as1106, as1107 austria micro systems data sheet note: see figure 11 on page 7 for more information. table 4. timing characteristics parameter symbol conditions min typ max unit clk clock period t cp 100 ns clk pulse width high t ch 50 ns clk pulse width low t cl 50 ns csm fall to clk rise setup time (as1107 or as1106 spi-programmed) t css 25 ns clk rise to load/csn rise hold time t csh 0ns din setup time t ds 25 ns din hold time t dh 0ns output data propagation delay t do c load = 50pf 25 ns load rising edge to next clock rising edge (as1106 only) t ldck 50 ns minimum load/csn pulse high t csw 50 ns data-to-segment delay t dspd 2.25 ms
www.austriamicrosystems.com revision 2.2 5 - 20 as1106, as1107 austria micro systems data sheet 6 typical operating characteristics v dd = 5v, r set = 9.53k , t amb = 25oc (unless otherwise specified). figure 2. scan frequency vs.temperature figure 3. scan frequency vs. v dd figure 4. i seg vs. temperature figure 5. i seg vs. v dd figure 6. as1106 segment output current fi gure 7. as1107 segment output current 900 910 920 930 940 950 960 970 980 23456 v dd (v) f osc (hz) 930 940 950 960 970 980 990 -40-20 0 20406080 t amb [c] f osc (hz) 0 5 10 15 20 25 30 35 40 45 50 -40-20 0 20406080 t amb (c) i seg (ma) 0 10 20 30 40 50 60 22.533.5 44.555.56 v dd (v) i seg (ma) v dd = 5v, v out = 2.4v v dd = 5v, v out = 4v v dd = 2.7v, v out = 2v v dd = 2.7v, v out = 2.4v v out = 1.7v v out = 2.4v v out = 4v intensity = 31/32 (0fh) 0 5 10 15 20 25 30 35 40 45 50 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 time (s ) i seg (ma) intensity = 15/16 (0fh) 0 5 10 15 20 25 30 35 40 45 50 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 time (s ) i seg (ma)
www.austriamicrosystems.com revision 2.2 6 - 20 as1106, as1107 austria micro systems data sheet figure 8. i seg vs. v out figure 9. i seg vs. v out figure 10. i seg vs. r set 0 5 10 15 20 25 30 35 40 45 50 00.511.522.533.544.55 v out (v) i seg (ma) v dd = 2.7v 0 5 10 15 20 25 00.511.522.5 v out (v) i seg (ma) r set = 10k r set = 20k r set = 40k r set = 40k r set = 10k r set = 20k 0 10 20 30 40 50 60 0 1020304050607080 r set (k ) i seg (ma) v out = 2.4v v out = 4v v out = 2v v out = 1.7v v dd = 2.7v v dd = 5v
www.austriamicrosystems.com revision 2.2 7 - 20 as1106, as1107 austria micro systems data sheet as1106 vs. as1107 7 detailed description as1106 vs. as1107 the as1106 and as1107 are identical except for two features: the as1107 segment drivers are slew-rate limited to reduce electromagnet ic interference (emi). the as1107 serial interface is fully spi compatible (programmable for as1106). serial-addressing format programming the as1106/as1107 is done by writing to the device?s internal re gisters (see digit- and control-registers on page 8) via the 4-wire serial interface. a programming s equence consists of 16-bit packages as listed in table 5. the data is shifted into the internal 16-b it register with the rising edge of the clk signal. with the rising edge of the load/csn signal the data is latched into a digit- or contro l-register. the load/csn signal must go high after the 16th rising clock edge. the load/csn signal can also come later but this must happe n just before the next rising edge of clk, otherwise the data will be lost. the contents of the internal shift register are applied 16.5 clock cycles later to pin dout. the data is clocked out at the falling edge of clk. the first 4 bits (d15:d12) are ?don't care?, bits d11:d8 co ntain the register address, and bits d7:d0 contain the data. the first bit is d15, the most significant bit (msb). the exact timing is shown in figure 11. initial power-up on initial power-up, the as1106/as1107 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. at this time, all registers should be programmed for normal operation. note: the default settings enable only scanning of one digit; t he internal decoder is disabl ed and the intensity control register (see page 11) is set to the minimum values. figure 11. interface timing table 5. 16-bit serial data format d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x register address (see table 6) msb data lsb t cl load/ csn clk din dout d15 d14 d1 d0 t do t css t ds t dh t ch t cp t csh t csw t ldck
www.austriamicrosystems.com revision 2.2 8 - 20 as1106, as1107 austria micro systems data sheet shutdown mode shutdown mode the as1106/as1107 devices feature a shutdown mode, where they consume only 10a (max) current. shutdown mode is entered via a write to the shutdown register (see table 7). for the as1106, at that point, all segment current sources are pulled to ground and all digit drivers are connected to v dd , so that all segments are blanked. the as1107 behavior is identical except the drivers are high impedance. note: during shutdown mode the digit-registers maintain their data. shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display (repeatedly entering and leaving shutdown mode). for minimu m supply current in shutdown mode, logic input should be at gnd or v dd (cmos logic level). the devices need typically 250s to exit shutdown mode, and during shutdown mode the as1106/as1107 is fully pro- grammable. only the display test mode (see page 10) overrides shutdown mode. when entering or leaving shutdown mode, th e feature register is reset to its def ault values (all 0s) when shutdown register bit d7 (page 9) = 0. 1 note: if the as1106/as1107 is used with an external clock, sh utdown register bit d7 should be set to 1 when writing to the shutdown register. digit- and cont rol-registers the as1106/as1107 devices contain 8 digit-registers and 6 cont rol-registers, which are listed in table 6. all registers are selected using a 4-bit address word, and communication is done via the serial interface. digit registers ? these registers are r ealized with an on-chip 64-bit memory. each digit can be controlled directly without rewriting the whole register contents. control registers ? these registers consist of decode mode, display intensity, number of scanned digits, shut- down, display test and feat ures selection registers. 1. when shutdown register bit d7 = 1, the feature register is left unchanged when entering or leaving shut- down mode. table 6. register address map register hex code address page d15:d12 d11 d10 d9 d8 no-op 0xx0 x000012 digit 0 0xx1 x 0 0 0 1 n/a digit 1 0xx2 x 0 0 1 0 n/a digit 2 0xx3 x 0 0 1 1 n/a digit 3 0xx4 x 0 1 0 0 n/a digit 4 0xx5 x 0 1 0 1 n/a digit 5 0xx6 x 0 1 1 0 n/a digit 6 0xx7 x 0 1 1 1 n/a digit 7 0xx8 x 1 0 0 0 n/a decode-mode 0xx9 x 1 0 0 1 9 intensity control 0xxa x 1 0 1 0 11 scan limit 0xxb x 1 0 1 1 11 shutdown 0xxc x 1 1 0 0 9 n/a 0xxd x1101n/a feature 0xxe x 1 1 1 0 12 display test 0xxf x 1 1 1 1 10
www.austriamicrosystems.com revision 2.2 9 - 20 as1106, as1107 austria micro systems data sheet digit- and control-registers shutdown register (0xxc) the shutdown register controls as1106/as1107 s hutdown mode (see shutdown mode on page 8). decode enable register (0xx9) the decode enable register sets the decode mode. bcd/hex decoding (either bcd code ? characters 0:9, e, h, l, p, and -, or hex code ? characters 0:9 and a:f) is sele cted by bit d2 (page 12) of the feature register. the decode enable register is used to select the decode mode or no -decode for each digit. each bit in the decode enable regis- ter corresponds to its respective display digit (i.e., bit d0 corresponds to digit 0, bit d1 corresponds to digit 1 and so on). table 9 lists some examples of the possible settings for the decode enable register bits. note: a logic high enables decoding and a logic low bypasses the decoder altogether. when decode mode is used, the decoder looks only at the lower-n ibble (bits d3:d0) of the data in the digit-registers, disregarding bits d6:d4. bit d7 sets the decimal point (seg dp) independent of the decoder and is positive logic (bit d7 = 1 turns the decimal point on). table 9 list s the code-b font; table 10 lists the hex font. when no-decode mode is selected, data bits d7:d0 of the digit-registers correspond to the segment lines of the as1106/as1107. table 11 shows the 1:1 pairing of each data bit to the appropriate segment line. figure 12. standard 7-segment led in tensity control and inter-digit blanking table 7. shutdown register format (address (hex) = 0xxc)) mode hex code register data d7 d6 d5 d4 d3 d2 d1 d0 shutdown mode, reset feature register to default settings 0x00 0xxxxxx0 shutdown mode, feature register unchanged 0x80 1xxxxxx0 normal operation, reset feature register to default settings 0x01 0xxxxxx1 normal operation, feature register unchanged 0x81 1 xxxxxx1 table 8. decode enable register format (address (hex) = 0xx9)) decode mode hex code register data d7 d6 d5 d4 d3 d2 d1 d0 no decode for digits 7:0 0x00 0000000 0 code-b/hex decode for digit 0. no decode for digits 7:1 0x01 00000001 code-b/hex decode for digits 3:0. no decode for digits 7:4 0x0f 00001111 code-b/hex decode for digits 7:0 0xff 11111111 table 9. code-b font 7-segment character register data on segments = 1 d7 ? d6:d4 d3 d2 d1 d0 dp ? a b c d e f g 0 x 0000 1111110 1 x 0001 0110000 2 x 0010 1101101 3 x 0011 1111001 4 x 0100 0110011 a b g f e d c dp
www.austriamicrosystems.com revision 2.2 10 - 20 as1106, as1107 austria micro systems data sheet digit- and control-registers display-test register (0xxf) the as1106/as1107 devices can operate in two modes: normal mode and display test mode. in display test mode all leds are switched on at maximum bri ghtness (duty cycle is 15/16 (as1106) or 31/32 (as1107). the devices remain in display-test mode until the display-test register is set for normal operation. note: all settings of the digit- and control-registers are maintained. 5 x 0101 1011011 6 x 0110 1011111 7 x 0111 1110000 8 x 1000 1111111 9 x 1001 1111011 - x 1010 0000001 e x 1011 1001111 h x 1100 0110111 l x 1101 0001110 p x 1110 1100111 blank x 1111 0000000 ? the decimal point is enabled by setting bit d7 = 1. table 10. hex font 7-segment character register data on segments = 1 d7 ? d6:d4 d3 d2 d1 d0 dp ? a b c d e f g 0 x 0 0 0 0 1111110 1 x 0 0 0 1 0110000 2 x 0 0 1 0 1101101 3 x 0 0 1 1 1111001 4 x 0 1 0 0 0110011 5 x 0 1 0 1 1011011 6 x 0 1 1 0 1011111 7 x 0 1 1 1 1110000 8 x 1 0 0 0 1111111 9 x 1 0 0 1 1111011 a x 1 0 1 0 1110111 b x 1 0 1 1 0011111 c x 1 1 0 0 1001110 d x 1 1 0 1 0111101 e x 1 1 1 0 1001111 f x 1 1 1 1 1000111 ? the decimal point is enabled by setting bit d7 = 1. table 11. no-decode mode data bits and corresponding segment lines d7 d6 d5 d4 d3 d2 d1 d0 corresponding segment line dp a b c d e f g table 12. display-test register format (address (hex) = 0xxf)) mode register data d7 d6 d5 d4 d3 d2 d1 d0 normal operation xxxxxxx0 display test mode xxxxxxx1 table 9. code-b font (continued) 7-segment character register data on segments = 1 d7 ? d6:d4 d3 d2 d1 d0 dp ? a b c d e f g
www.austriamicrosystems.com revision 2.2 11 - 20 as1106, as1107 austria micro systems data sheet digit- and control-registers intensity control register (0xxa) the brightness of the display can be controlled by digital m eans using the intensity control register and by analog means using r set (see selecting rset resistor value and using external drivers on page 13). display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the intensity control register. the modulat or scales the average segment-current in 16 steps from a maximum of 31/32 down to 1/32 (15/16 to 1/16 for the as1107) of the peak current set by r set . scan-limit register (0x0b) the scan-limit register controls which of the digits are to be displayed. when all 8 digits are to be displayed, the update frequency is typically 800hz. if the number of digits displayed is r educed, the update frequency is increased. the frequency can be calculated using 8fosc/n, where n is the number of digits. since the number of displayed digits influences the brightness, r set should be adjusted accordingly. table 15 lists the maximum allowed current when fewer than 4 digits are used. note: to avoid differences in brightness this register should not be used to blank parts of the display (leading zeros). table 13. intensity register format (address (hex) = 0xxa)) duty cycle hex code register data as1106 as1107 d7 d6 d5 d4 d3 d2 d1 d0 1/32 (min on)1/16 (min on) 0xx0 xxxx 0000 3/32 2/16 0xx1 xxxx 0001 5/32 3/16 0xx2 xxxx 0010 7/32 4/16 0xx3 xxxx 0011 9/32 5/16 0xx4 xxxx 0100 11/32 6/16 0xx5 xxxx 0101 13/32 7/16 0xx6 xxxx 0110 15/32 8/16 0xx7 xxxx 0111 17/32 9/16 0xx8 xxxx 1000 19/32 10/16 0xx9 xxxx 1001 21/32 11/16 0xxa xxxx 1010 23/32 12/16 0xxb xxxx 1011 25/32 13/16 0xxc xxxx 1100 27/32 14/16 0xxd xxxx 1101 29/32 15/16 0xxe xxxx 1110 31/32 (max on)15/16 (max on) 0xxf xxxx 1111 table 14. scan-limit register format (address (hex) = 0xxb)) scan limit hex code register data d7 d6 d5 d4 d3 d2 d1 d0 display digit 0 only (see table 15) 0xx0 xxxxx0 0 0 display digits 0:1 (see table 15) 0xx1 xxxxx0 0 1 display digits 0:2 (see table 15) 0xx2 xxxxx0 1 0 display digits 0:3 0xx3 xxxxx0 1 1 display digits 0:4 0xx4 xxxxx1 0 0 display digits 0:5 0xx5 xxxxx1 0 1 display digits 0:6 0xx6 xxxxx1 1 0 display digits 0:7 0xx7 xxxxx1 1 1 table 15. maximum segment current for 1-, 2-, or 3-digit displays number of digits displayed maximum segment current (ma) 110 220 330
www.austriamicrosystems.com revision 2.2 12 - 20 as1106, as1107 austria micro systems data sheet digit- and control-registers feature register (0xxe) the feature register is used for enablin g various features including switching the device into external clock mode, applying an external reset, selecting code-b or hex decoding, enabling or disabling blinking, enabling or disabling the spi-compatible interface (as1106 only), setting th e blinking rate, and resetting the blink timing. note: at power-up the feature register is initialized to 0. no-op register (0xx0) the no-op register is used when multiple as1106 or as1107 devices are cascaded in order to support displays with more than 8 digits. the cascading must be done in such a way that all dout pins are connected to din of the next as1106/as1107 (see figure 13 on page 15). the load /csn and clk signals are connected to all devices. for example, if five devices are cascaded, in order to perf orm a write operation to the fifth device, the write-command must be followed by four no-operation commands. when the load/csn signal goes high, all shift registers are latched. the first four devices will re ceive no-operation commands and only the fifth device will receive the intended operation command, and subseq uently update its register. table 16. feature register summary d7 d6 d5 d4 d3 d2 d1 d0 blink_ start sync blink_ freq_sel blink_en spi_en decode_sel reg_res clk_en table 17. feature register bit descriptions (address (hex) = 0xxe)) addr: 0xxe feature register enables and disables various device features. bit bit name default access bit description d0 clk_en 0r/w external clock active. 0 = internal oscillator is used for system clock. 1 = pin clk of the serial interface operates as system clock input. d1 reg_res 0r/w resets all control registers except the feature register. 0 = reset disabled. normal operation. 1 = all control registers are reset to default state (except the feature register) identically after power-up. note: the digit registers maintain their data. d2 decode_sel 0r/w selects display decoding. 0 = enable code-b decoding (see table 9 on page 9). 1 = enable hex decoding (see table 10 on page 10). d3 spi_en 0r/w enables the spi-compatible interface. 0 = disable spi-compatible interface (as1106 only). 1 = enable the spi-compatible interface (as1106 only). note: the spi-compatible interface is always enabled in the as1107. d4 blink_en 0r/w enables blinking. 0 = disable blinking. 1 = enable blinking. d5 blink_freq_sel 0r/w sets blink with low frequency (with the internal oscillator enabled): 0 = blink period typically is 1 second (0.5s on, 0.5s off). 1 = blink period is 2 seconds (1s on, 1s off). d6 sync 0r/w synchronizes blinking on the rising edge of pin load/csn. the multiplex and blink timing counter is cleared on the rising edge of pin load/csn. by setting this bit in multiple as1106/as1107 devices, the blink timing can be synchronized across all the devices. d7 blink_start 0r/w start blinking with display enabled phase. when bit d4 (blink_en) is set, bit d7 determines how blinking starts. 0 = blinking starts with the display turned off. 1 = blinking starts with the display turned on.
www.austriamicrosystems.com revision 2.2 13 - 20 as1106, as1107 austria micro systems data sheet supply bypassing and wiring 8 typical application supply bypassing and wiring in order to achieve optimal performance the as1106/as1107 sh ould be placed very close to the led display to mini- mize effects of electromagnetic interference and wiring inductance. furthermore, it is recommended to connect a 10f electrolytic and a 0.1f ceramic capacitor between pins v dd and gnd to avoid power supply ripple (see figure 13 on page 15). note: both gnd pins must be connected to ground. selecting r set resistor value and us ing external drivers brightness of the display s egments is controlled via r set . the current that flows between v dd and i set defines the current that flows through the leds. segment current is about 200 times the current in i set . typical values for r set for different segment currents, operat- ing voltages, and led voltage drop (v led ) are given in tables 18 - 22. the maximum current the as1106/as1107 devices can drive is 40ma. if higher currents are needed, exter nal drivers must be used, in which case it is no longer necessary that the devices drive high currents. in cases where the devices only drive a few digits, table 15 specifies the maximum currents, and r set must be set accordingly. note: the display brightness can also be logically controlled (see intensity c ontrol register (0xxa) on page 11). table 18. r set vs. segment current and led forward voltage, v dd = 2.7v i seg (ma) v led (v) 1.5 2.0 40 5k 4.4k 30 6.9k 5.9k 20 10.7k 9.6k 10 22.2k 20.7k table 19. r set vs. segment current and led forward voltage, v dd = 3.3v i seg (ma) v led (v) 1.5 2.0 2.5 40 6.7k 6.4k 5.7k 30 9.1k 8.8k 8.1k 20 13.9k 13.3k 12.6k 10 28.8k 27.7k 26k table 20. r set vs. segment current and led forward voltage, v dd = 3.6v i seg (ma) v led (v) 1.5 2.0 2.5 3.0 40 7.5k 7.2k 6.6k 5.5k 30 10.18k 9.8k 9.2k 7.5k 20 15.6k 15k 14.3k 13k 10 31.9k 31k 29.5k 27.3k table 21. r set vs. segment current and led forward voltage, v dd = 4.0v i seg (ma) v led (v) 1.5 2.0 2.5 3.0 3.5 40 8.6k 8.3k 7.9k 7.6k 5.2k 30 11.6k 11.2k 10.8k 9.9k 7.8k
www.austriamicrosystems.com revision 2.2 14 - 20 as1106, as1107 austria micro systems data sheet calculating power dissipation calculating power dissipation the upper limit for power dissipation (pd) for the as1106/as1107 is determined from the following equation: pd = (v dd x 1ma) + (v dd - v led )(duty x i seg x n) (eq 1) where: v dd is the supply voltage. duty is the duty cycle set by intensity register (page 11). n is the number of segments driven (worst case is 8) v led is the led forward voltage i seg = segment current set by rset dissipation example: i seg = 40ma, n = 8, duty = 31/32, v led = 1.8v at 40ma, v dd = 5.25v (eq 2) pd = 5.25v(1ma) + (5.25v - 1.8v)(31/32 x 40ma x 8) = 1.075w (eq 3) thus, for a pdip package ja = +75c/w (from table 23) , the maximum allowed t amb is given by: t j,max = t amb + pd x ja = 150c = t amb +1.07w x 75c/w (eq 4) where: t amb = +69.4c. the t amb limit for so packages in the di ssipation example above is +58.6c. 20 17.7k 17.3k 16.6k 15.6k 13.6k 10 36.89k 35.7k 34.5k 32.5k 29.1k table 22. r set vs. segment current and led forward voltage, v dd = 5.0v i seg (ma) v led (v) 1.5 2.0 2.5 3.0 3.5 4.0 40 11.35k 11.12k 10.84k 10.49k 10.2k 9.9k 30 15.4k 15.1k 14.7k 14.4k 13.6k 13.1k 20 23.6k 23.1k 22.6k 22k 21.1k 20.2k 10 48.9k 47.8k 46.9k 45.4k 43.8k 42k table 23. package thermal data package thermal resistance ( ja ) 24 narrow dip +75c/w 24 wide soic +85c/w table 21. r set vs. segment current and led forward voltage, v dd = 4.0v (continued) i seg (ma) v led (v) 1.5 2.0 2.5 3.0 3.5
www.austriamicrosystems.com revision 2.2 15 - 20 as1106, as1107 austria micro systems data sheet 8x8 led dot matrix driver 8x8 led dot matrix driver the application example in figure 13 shows the as1106 as an 8x8 led dot matrix driver. the led columns have common cathodes and are connected to the dig0:7 outputs. the rows are connected to the segment drivers. each of the 64 leds can be addressed sepa rately. the columns are selected via the digits as listed in table 6 on page 8. the decode enable register (see page 9) must be set to ?00000000? as described in table 8 on page 9. single leds in a column can be addressed as described in table 11 on page 10, where bit d0 corresponds to segment g and bit d7 corresponds to segment dp. note: for a multiple-digit dot matrix, multiple as1106 devices must be cascaded. figure 13. application example as led dot matrix driver cascading drivers the example in figure 4 drives 2 dot matrix digits using a 4-wire microprocessor interfac e. all scan-limit registers should be set to the same value so that one display will not appear brighter than the other. for example, to display 12 digits, set both scan-limit regist ers to display 6 digits so that both displays have a 1/6 duty cycle per digit. if 11 digits are need ed, set both scan-limit regist ers to display 6 digits and leave one digit uncon- nected. otherwise, if one driver is set to disp lay 6 digits and the other to display 5 digits one display will appear brighter because its duty cycle per digit will be 1/5 and the other display?s duty cycle will be 1/6. note: refer to no-op register (0xx0) on page 12 for additional information. seg g dig0:7 i set din gnd gnd load/csn clk v dd seg a:g seg dp 9.53k dig0:7 i set din gnd gnd load/csn clk v dd seg a:g seg dp 9.53k dout 8x8 led dot matrix 8x8 led dot matrix diode arrangement v bat v bat micro- processor seg a seg dp seg b seg c seg d seg e seg f seg g seg a seg dp seg b seg c seg d seg e seg f
www.austriamicrosystems.com revision 2.2 16 - 20 as1106, as1107 austria micro systems data sheet pin assignments 9 pinout and packaging pin assignments figure 14. dip and so pin assignments (top view) pin descriptions table 24. pin descriptions pin name pin number description din 1 serial-data input . data is loaded into the internal 16-bit shift register on the rising edge of pin clk. dig 0:dig 7 2, 3, 5, 6, 7, 8, 10, 11 digit drive lines . 8 eight-digit drive lines that sink current from the display common cathode. the as1106 pulls the digit outputs to v dd when turned off. the as1107 digit drivers are high-impedance when turned off. gnd 4, 9 ground . both gnd pins must be connected. load/csn 12 load-data input (as1106 only). the last 16 bits of serial data are latched on the rising edge of this pin. chip-select input (as1107 or as1106 spi-enabled only). serial data is loaded into the shift register while this pin is low. the last 16 bits of serial data are latched on the rising edge of this pin. clk 13 serial-clock input . 10mhz maximum rate. data is shifted into the internal shift register on the rising edge of this pin. data is clocked out of pin dout on the falling edge of this pin. on the as1107 or as1106 spi-enabled, the clk input is active only while load/csn is low. seg a:seg g, seg dp 14, 15, 16, 17, 20, 21, 22, 23 seven segment and decimal point drive lines . 8 seven-segment drives and decimal point drive that source cu rrent to the display. on the as1106, when a segment driver is turned off it is pulled to gnd. the as1107 segment drivers are high-impedance when turned off. i set 18 set segment current . connect to v dd through r set to set the peak segment current (see selecting rset resistor value and using external drivers on page 13). v dd 19 positive supply voltage . connect to +2.7 to +5.5v supply. dout 24 serial-data output . the data into pin din is valid at pin dout 16.5 clock cycles later. this pin is used to daisy-chain several as1106/as1107 devices and is never high-impedance. 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 dout seg d seg dp seg e seg c v dd i set seg g seg b seg f seg a clk din dig 0 dig 4 gnd dig 6 dig 2 dig 3 dig 7 gnd dig 5 dig 1 load/csn as1106/ as1107
www.austriamicrosystems.com revision 2.2 17 - 20 as1106, as1107 austria micro systems data sheet package drawings and markings package drawings and markings the as1106 and as1107 are available in 24-pin dip and 24-pin soic packages. figure 15. 24-pin dip package symbol min max b0.18 b1 0.015 c0.10 d1.160 d1 0.30 0.60 e.295.320 id 0.64 id1 0.64 e1 .260 ea .320 .370 e1 1.00 l.125 r.030 t.130 t1 .060 t2 .060 w .030 ref 1 7o 2 7o 3 7o 4 7o p? .760 a.145.170 a1 .015 .040
www.austriamicrosystems.com revision 2.2 18 - 20 as1106, as1107 austria micro systems data sheet package drawings and markings figure 16. 24-pin soic package notes: 1. controlling dimension is millimeters. symbol min max symbol min max a 2.44 2.84 h 10.11 10.51 a1 0.10 0.30 h 0.31 0.71 a2 2.24 2.44 j 0.53 0.73 b 0.36 0.46 k 7o bsc c 0.23 0.32 l 0.51 1.01 d 12.65 12.85 r 0.63 0.89 e 7.40 7.50 zd 0.66 ref e 1.27 bsc 0o 8o
www.austriamicrosystems.com revision 2.2 19 - 20 as1106, as1107 austria micro systems data sheet 10 ordering information the as1106 and as1107 are available in 24-pin dip and 24-pin soic packages. table 25. ordering information part temperature range delivery form package as1106pl 0 to +70c tubes 24-pin narrow plastic dip, pb-free as1106wl 0 to +70c tubes 24-pin wide so, pb-free as1106wl-t 0 to +70c tape and reel 24-pin wide so, pb-free as1106pe -40 to +85c tubes 24-pin narrow plastic dip, pb-free as1106we -40 to +85c tubes 24-pin wide so, pb-free as1106we-t -40 to +85c tape and reel 24-pin wide so, pb-free AS1107PL 0 to +70c tubes 24-pin narrow plastic dip, pb-free as1107wl 0 to +70c tubes 24-pin wide so, pb-free as1107wl-t 0 to +70c tape and reel 24-pin wide so, pb-free
www.austriamicrosystems.com revision 2.2 20 - 20 as1106, as1107 austria micro systems data sheet copyrights copyright ? 1997-200 5, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the materi al herein may not be reprodu ced, adapted, merged, trans- lated, stored, or used witho ut the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from pa tent infringement. austriami- crosystems ag reserves the right to chang e specifications and prices at any ti me and without notice . therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial a pplications. applications requiring extended temperature range, unusual environmental requirements, or high reliability app lications, such as military, medical life-support or life- sustaining equipment are specifically not recommended wit hout additional processing by austriamicrosystems ag for each application. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or ar ising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 e-mail: info@austriamicrosystems.com for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com austria micro systems ? a leap ahead

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